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Ordering number : EN*A0906A
LC074146LP
Overview
CMOS IC
Monaural CODEC+Audio I/F +Video driver IC
The LC074146LP is an IC that integrates a video driver with audio CODEC developed for digital still cameras and other portable equipment. Incorporating 16-bit A/D and D/A converters as well as a microphone amplifier and speaker driver that are necessary for audio recording and playback, the one-chip IC is ideal for use to create audio interfaces.
Features and Functions
Audio Block * method 16-bit monaural A/D and D/A converters * Generates bias voltage (2.3V) for microphone * Supports microphone amplifier differential inputs (0/+20/+26dB) * Amplifier with automatic level control (ALC)(-14dB to +34dB) for recording system * Programmable digital filter * Digital volume with automatic level control (ALC) for playback system Supports zerocross detection and soft switching * Line output Onchip MUTE and POP-noise suppression circuits * Speaker driver Supports SVDD=5V (piezoelectric speaker supported) BTL drive, rated output of 350mW at 8, SVDD=3V Idling current adjustable Supports BEEP input, volume level switchable * Audio interfaces I2S, Left-justified mode, Right-justified mode * PLL Input: 12MHz, 13.5MHz, 24MHz, 27MHz Sampling frequency: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz PLL master mode/slave (EXT) mode * Loopback: ADOUT to DAIN switch incorporated
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
O0307 TI IM No.A0906-1/31
LC074146LP
Video Block * DC direct coupling input/output * Built-in 6th order low-pass filter (fc=7.5MHz) * Amplifier gain selectable (6dB or 12dB) * Drive capacity 75, 1 system * 3-line serial register control * Supply voltage: 3.0V (2.7 to 3.6V) * Operating ambient temperature: -15 to +80C
Package Dimensions
unit : mm (typ) 3302A
Top View Bottom View
0.35 5.0 21 20 5.0 30 0.35 (0.7) 31
0.4
40 11 10 0.85MAX 0.2 1 (0.7)
0.05 0 NOM
SANYO : VQLP40(5.0X5.0)
Sample Application Circuit
MCKLIN VSSSUB
VCOFIL
MICOUT
MCLKO
VDDP
ALCIN
VSSP
BCLK
MIC
SPOUTP
VIDEOVREF
VDDV
VIDEOOUT
SPOUTN
VDDS
VSSS
VIDEOIN
PDNB
VSSV
LRCK
No.A0906-2/31
LC074146LP
Circuit Block Diagram
VIDEOIN 0dB -6/0dB REG VREF1 VREF2 BEEP LPF
+12dB
VIDEOOUT
to Speaker SPOUTP AMP control SPOUTN
MICINN
SPKIN
MIC
MICINP
MIC Pre-Amp
Select LOUT2
MIC Power MICOUT
ALCIN PGA ADC 16bit D_VOL FLT * HPF * Notch * HSF Inter -Face DAC 16bit
LOUT1
ALC cont.
ALC/Limiter
VREF
MCLKO
MPU
MCLKIN MAX:27MHz BCLK
1/1 1/2
a b PLL MAX:13.5MHz B
256fs Audio_Format IF 2 (I S, Left-justified mode, Right-justified mode) BCLK: 64fs/32fs
1/8,1/4
a 32fs b 64fs a fs b
1/256 LRCLK DAIN ADOUT CSB SCK SDA B
Serial IF /Register/
n
PDNB
MCLKO(system clock) MAX: 256fs=256x48kHz =12.288MHz
No.A0906-3/31
LC074146LP
Pin Assignment
40 39 38 37 36 35 34 33 32 31 LRCK BCLK MCLKO MCLKIN VSSP VDDP VCOFIL VSSSUB ALCIN MICOUT
1 2 3 4 5 6 7 8 9 10
MICPWR MICINP MICINN VDDA VREF VSSA LOUT1 LOUT2 SPKIN BEEP
ADOUT DAIN DVDD DVSS TESTIN GPORT1 GPORT0 SDA SCK CSB
30 29 28 27 26 25 24 23 22 21
11 12 13 14 15 16 17 18 19 20
PDNB VIDEOVREF VIDEOOUT VSSV VDDV VIDEOIN SPOUTP VSSS VDDS SPOUTN
Pin Description
(Note) I/O: I=> input, Is=> Schmitt input, O=> output, IOs=> input/output
PIN No Digital system 20 21 22 23 24 25 26 29 30 31 32 33 34 Is I Is Is IOs IOs Is Is O IOs IOs O I PDNB CSB SCK SDA GPORT0 GPORT1 TESTIN DACIN ADOUT LRCK BCLK MCLKO MCLKIN Reset (negative polarity) Chip select (negative polarity) Serial clock Serial data input Microcontroller IF I/O Symbol Conditions
Microcontroller IF Microcontroller IF
For IC testing (open in normal operation) For IC testing (open in normal operation) Test input (VSS fixed in normal operation) DAC serial data input ADC serial data output LR clock input Bit clock input Master clock output (Default: Set to Low, serial setting enables output/Add; 0Dh) Master clock input
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No.A0906-4/31
LC074146LP
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PIN No Analog system 11 14 15 18 19 37 39 40 1 2 3 5 7 8 9 10 Power supply 12 13 16 17 27 28 35 36 38 4 6 VDDS VSSS VDDV VSSV DVSS DVDD VSSP VDDP VSSSUB VDDA VSSA Speaker analog power supply Speaker analog ground Video driver analog power supply Video driver ground Digital ground (0V) Digital power supply (3V) PLL ground (0V) PLL power supply (3V) Subground (0V) Analog block power supply (3V) Analog block ground (0V) O O I O O O I O O I I O O O I I SPOUTN SPOUTP VIDEOIN VIDEOOUT VIDEOVREF VCOFIL ALCIN MICOUT MICPWR MICINP MICINN VREF LOUT1 LOUT2 SPKIN BEEP Speaker output (-) Speaker output (+) Video signal input Video signal output Video VREF VCO filter pin ALC amplifier input Microphone amplifier output Microphone power supply output (2.3V) Microphone amplifier input (+ side) Microphone amplifier input (- side) 3V analog power supply reference voltage output Line output 1 Line output 2 Speaker amplifier input BEEP signal input, mixed to speaker amplifier I/O Symbol Conditions
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage (5V system) Maximum supply voltage (3V system) Input voltage Output voltage Input/output voltage Allowable operating voltage range Symbol VDD5 max VDD3 max VIN max VOUT max VIO max VRANGE VDDSrange Allowable power dissipation Operating ambient temperature Storage ambient temperature Pd max Topr Tstg * Ta=80C Other than VDDS Conditions Ratings -0.3 to 7.0 -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 2.7 to 3.6 2.7 to 5.5 TBD -15 to +80 -55 to +125 mW C C V V V V unit V
* Mounted on a specified board: 40mmx50mmx0.8mm, glass epoxy board 2S2P (4-layer board)
No.A0906-5/31
LC074146LP
Recommended Operating Range at VSSV=DVSS=VSSP=VSSA=VSSSUB=0V
Parameter Supply voltage Symbol DVDD VDDana VDDS Inpupt high level voltage Input low voltage level voltage Input clock frequency Input clock duty VIH VIL fMCLK DutyMCLK DVDD pin VDDV, VDDP, VDDA, pin VDDS pin (*1) (*1) MCLKIN pin MCLKIN pin 0.45 0.50 Conditions min 2.7 2.7 2.7 0.8*DVDD VSS Specification typ 3.0 3.0 3.0/5.0 max 3.6 3.6 5.5 DVDD 0.2*DVDD 27 0.55 unit V V V V V MHz %
(*1) Applicable pins: PDNB, CSB, SCK, SDA, GPORT0, GPORT1, TESTIN, DAIN, LRCK, BCLK, MCLK BCLK, LRLK (in input mode), GPORT1-0 (in input mode, only output mode during normal operation) Electrical Characteristics at Ta=252C,VDDana=DVDD=VDDS=2.7to 3.6V,VSSV=DVSS=VSSP=VSSA=VSSSUB=0V
Parameter Input high level current Inputp low level current Output high level voltage Output low level voltage Symbol IIH IIL VOH1 VOL1 VI=DVDD(*1) VI=DVSS(*1) IOH=-1mA(*2) IOL=1mA(*2) -1 0.8*DVDD 0.2*DVDD Conditions min Specification typ max +1 unit A A V V
(*1) Applicable pins: MCLKIN, TESTIN, PDNB, CSB, SCK, SDA, BCLK, LRCK (in input mode), GPORT1-0 (in input mode, only output mode during normal operation) (*2) Applicable pins: ADOUT, BCLK, LRCK (in output mode), GPORT1-0 (in input mode, only output mode during normal operation) Analog Characteristics at Ta=+25C,VDDA=DVDD=VDDS=VDDV=VDDP=3.0V,fs=48kHz
Parameter Current drain REC time analog system REC time digital system PB(LINE) time analog system PB(LINE) time digital system PB(SPK) time analog system PB(SPK) time digital system Video block 1 Video block 2 Power down time current MIC MIC amplifier gain VGmic MGAIN[1:0]=01 MGAIN[1:0]=10 MGAIN[1:0]=11 MIC amplifier output THD+N MIC amplifier output noise voltage MIC bias output voltage ALC Gain change Gain control range DGalc VGalc -14 1 +34 dB dB Vmicpwr RL=5k THDNmic VNOmic VIN=-30dBV, MGAIN[1:0]=11 MIC IN no signal, A-weighted, MGAIN[1:0]=11 0 20 26 -80 -88 2.3 -70 dB dBV V dB IDDRA1 IDDRD1 IDDPA2 IDDPD2 IDDPA3 IDDPD3 IDDA1 IDDD1 IDDPD VDDA+VDDP+VDDS, no input signal DVDD VDDA+VDDP+VDDS, no input signal DVDD VDDA+VDDP+VDDS, no input signal DVDD VDDV, no input signal VDDV, Video in=white50% VDDA+VDDS+VDDV+DVDD+VDDP, clock stopped TBD TBD TBD TBD TBD TBD TBD TBD 10 mA mA mA mA mA mA mA mA A Symbol Conditions min Specification typ max unit
ADC ALCIN input, ALCOFF Gain=0dB Analog input voltage THD+N Dynamic range S/N ratio Vinad THDNad DRad SNad 0dBFS, 1kHz -1dBFS, 1kHz -60dBFS, A-weighted ALCIN no signal, A-weighted 0.6VDDA 80 86 86 Vpp dB dB dB
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No.A0906-6/31
LC074146LP
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Parameter DAC Digital volume change DGvol1 DGvol2 DGvol3 LINE DACLINE Gain=0dB, DVOL=0dB Analog output voltage THD+N Dynamic range S/N ratio SPK SPK amplifier gain SPK output distortion SPK output noise voltage SPK maximum rated output BEEP gain VGsp HDsp VNOsp VOMsp VGbp BTL, RL=8 SPKIN=-9dBV SPKIN no signal, RL=8 RL=8, THD=3% BTL, RL=8 BPVOL[1:0]=00 BPVOL[1:0]=01 BPVOL[1:0]=10 BPVOL[1:0]=11 Video driver Video amplifier gain Frequency characteristics Input impedance Input sync-tip level VGvideo Fva Rvin Vsync VGAIN[1:0]=00, Video in=1Vp-p100% white VGAIN[1:0]=10, Video in=0.5Vp-p100% white f=6MHz/100kHz f=20MHz/100kHz 100 -1 6 12 0 -45 120 0 50 +1 dB dB k mV 12 0.2 -86 350 -12 -15 -18 -21 dB 1 dB % dBV mW Voutda THDNda DRda SNda 0dBFS, 1kHz 0dBFS, 1kHz -60dBFS, A-weighted A-weighted 0.6VDDA 85 88 88 Vp-p dB dB dB +12dB to -10dB -11dB to -42dB -44dB to -64dB 0.5 1 2 dB dB dB Symbol Conditions min Specification typ max unit
ADC Filter Characteristics (fs=48kHz)
Parameter Resolution Passband 0.04dB 0.06dB 0.09dB Stopband Passband ripple Stopband attenuation Output data delay HPF cutoff frequency -3dB 0to 20kHz -60 40 0.94 0 0 0 24 0.09 Conditions min Specification typ 16 19.6 20.7 21.8 max unit Bit kHz kHz kHz kHz dB dB 1/fs Hz 1st order IIR high pass filter 0.4535fs 0.5fs Remarks
DAC Filter Characteristics (fs=48kHz)
Parameter Resolution Passband Stopband Passband ripple Stopband attenuation Output data delay HPF cutoff frequency -3dB -80 31 0.94 Note 1 0 26.2 0.002 Conditions min Specification typ 16 21.8 max unit Bit kHz kHz dB dB 1/fs Hz 1st order IIR high pass filter 0.4535fs 0.5465fs Remarks
No.A0906-7/31
LC074146LP
Switching Characteristics
Parameter PLL CKIN frequency fCKI PLL used EXT input present BCLK frequency fBCK FBCK=0 FBCK=1 BCLK duty cycle LRCK frequency LRCK duty cycle CLK transition time CLK transition time dtBK fLR dtLR trCK tfCK Rise time, CKIN/BCLK/LRCK inputs present Fall time, CKIN/BCLK/LRCK inputs present 45 8 45 50 12 2.048 64fs 32fs 50 55 48 55 10 10 % kHz % ns ns 27 24.576 MHz MHz Symbol Conditions min Specification typ max unit
Parameter Microcontroller serial interface timing SCLK cycle time SCLK High period SCLK Low period Data setup time Data hold time CSX rise to SCLK wait time SCLK to CSX rise wait time Rise time Fall time Audio data timing Clock phase (Note 2) Clock phase (Note 3) Data delay time Data setup time Data hold time
Symbol min typ
Specification max unit
tCYC tSH tSL tSU tHD tWSCLK tWCSX tSR tSF
4T 2T 2T 2T 2T 0T 4T
8T 4T 4T 4T 4T 2T 6T 50 50
ns ns ns ns ns ns ns ns ns
tPH tPH tDD tSUA tHDA
75 1/(128fs) 0 TBD TBD 75
ns ns ns ns ns
Note 1: T=1/fMCLK, fMCLK: Frequency of MCLKIN pin; example: when fMCLK=10MHz, T=100ns, 2T=200ns Note 2: LRCK and BCLK are inputs in Slave mode. The MCLK timing needs only to be synchronized with LRCK and BCLK and its phase is irrelevant. Note 3: In master mode, LRCK and BCLK are output in master mode and fs is the sampling frequency. Note 4: The load of output pin: 30pF. Microcontroller Serial Interface Timing Diagram
CSB tWSCLK tSH SCK tSU SDA tHD tSF tSR Dn[0] tCYC tSL tWCSX
A[7]
No.A0906-8/31
LC074146LP
Audio Data Timing Diagram
LRCK tPH BCLK tDD ADOUT tSU DAIN tHD tPH
Audio Data Formats * I2S mode
LRCK BCLK ADOUT 15 14 ** ** 1 0 ** 15 14 ** 1 Rch Data 0 **
Lch Data
* Left-justified mode
LRCK BCLK ADOUT 15 14 *** *** 1 0 *** 15 14 *** *** Rch Data 1 0 *** 15
Lch Data
* Right-justified mode
LRCK BCLK ADOUT 0 *** 15 *** 14 * * * 1 Lch Data 0 *** 15 14 *** *** 1 0
Rch Data
Pin Name MCLKIN MCLKO
PIN No. 34 33
Slave Mode (PLL: OFF) Input Output (through)
Master Mode (PLL: ON) Input Output (PLL=256fs)
Pin Name LRCK BCLK
PIN No. 31 32
Slave Mode Input Output
Master Mode Input Output
No.A0906-9/31
LC074146LP
Pins' Internal Equivalent Circuits * Digital pins
P34 MCLKIN P26 TESTIN schmitt P20 PDNB P21 CSB P22 SCK P23 SDA P29 DAIN schmitt S S P32 BCLK P31 LRCK P24 G_PORT0 P25 G_PORT1 P30 ADOUT P33 MCLKO
* Analog pins Note: All resistance values are typical values. Video driver related pins
120k P15 VIN 120k P19 VIDEO VREF P18 VIDEO OUT
Speaker input/output pins
P10 BEEP
225k P14 SPOUTP P11 SPOUTN 5k 10k
P9 SPKIN
VREF
LINE_OUT
MIC input
P2 MICINP P5 VREF P7 LOUT1 P8 LOUT2
70k
70k P3 MICINN
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No.A0906-10/31
LC074146LP
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MIC power supply
MIC output
ALC input
P1 MICPWR
P40 MICOUT
P39 ALCIN
20k
PLL detector
100
P37 VCOFIL
Microcontroller Serial Interface
The internal registers values are written by the serial interface consisting of the three CSB, SCK, and SDA lines. When the CSB pin is set low, the LC074146LP is switched into the mode that enables operation. The data is received on a byte basis with MSB first. Continuous access (burst access) is also possible, and the addresses incremented by 1 are accessed in sequence with each byte following access to the register specified by the address byte. If the size of data exceeding the highest address (0E) is accessed in this process, the data concerned is treated as invalid. In other word, the address never wraps around to 00 (HEX). Transferring data to one address A[7:0] : Designated address D[7:0] : Register data X : Invalid
CSB SCK SDA X X A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] ADDRESS BYTE D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] WRITE DATA (address A) X X
Transferring data to contiguous addresses
CSB SCK SDA X X
A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] Dn[0]
X X
ADDRESS BYTE
WRITE DATA (address)
WRITE DATA (address)
No.A0906-11/31
LC074146LP
Register Table
ADRS (Address): displayed in hexadecimal notation, Init (initial value): displayed in hexadecimal notation Register bits indicated by "0" must be set to 0 and those indicated by "1" must be set to 1. Registers indicated with a gray background are for IC testing and their initial values are fixed. All registers (addresses: 00 to 25h) must be loaded with write data (including test registers).
Functions PM1 PM2 MIC/SEL ALC1 ALC2 ALC3 ALC4 TEST0 CODEC1 CODEC2 CODEC3 EVR1 EVR2 MCLK LO/SPK1 SPK2 VIDEO FS PLL LPF_HSF Notch_1 Notch_1 Notch_2 Notch_2 Notch_3 Notch_3 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 ADRS [7:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h Init 7 00h 00h 11h 3Dh 46h 0Eh 0Eh 04h 02h 00h 00h 80h 54h 00h E0h 88h 02h 08h 00h 00h 00h 00h 00h 00h 00h 00h 00h 01h 00h 02h 03h 18h 00h B0h 21h 00h 00h 00h MIC_PDX SYNC_CLR 0 ALC_VAL[2] ALC_FULLEN 0 0 0 HSF_ON 0 0 EVR_MUTE 0 0 LO_MUTE SP_TSD_EN 0 0 0 0 A[15] A[7] B[15] B[7] C[15] C[7] 0 0 0 0 0 0 0 1 0 0 0 0 6 MIC_PWR_PDX 0 0 ALC_VAL[1] ALC_ZCD 0 0 0 NOTCH_ON 0 0 EVR_GAIN[6] EVR_ZCD 0 LO_VREFSW SP_EXTBP_EN 0 0 0 0 A[14] A[6] B[14] B[6] C[14] C[6] 0 0 0 0 0 0 0 0 0 0 0 0 5 PGA_PDX VREF_BIAS[1] MIC_GAIN[1] ALC_VAL[0] ALC_ZCDTM[1] ALC_VMAX[5] ALC_GAIN[5] 0 WIND_CUT[1] 0 0 EVR_GAIN[5] EVR_ZCDTM[1] 0 LO_GAIN[1] SP_EXTBP_G[1] VD_GAIN 0 0 0 A[13] A[5] B[13] B[5] C[13] C[5] 0 0 0 0 0 0 0 1 1 0 0 0 Register Data D[7:0] 4 ADC_PDX VREF_BIAS[0] MIC_GAIN[0] ALC_FA[1] ALC_ZCDTM[0] ALC_VMAX[4] ALC_GAIN[4] 0 WIND_CUT[0] ADF_MASTER 0 EVR_GAIN[4] EVR_ZCDTM[0] 0 LO_GAIN[0] SP_EXTBP_G[0] VD_DCTL2[1] FS[4] 0 0 A[12] A[4] B[12] B[4] C[12] C[4] 0 0 0 0 0 1 0 1 0 0 0 0 3 DAC_PDX 0 0 ALC_FA[0] ALC_TLIM[1] ALC_VMAX[3] ALC_GAIN[3] 0 AD_MUTE ADF_DAC_INV 0 EVR_GAIN[3] 0 SEL_MCLKO[1] 0 SP_IDL[1] VD_DCTL2[0] FS[3] 0 0 A[11] A[3] B[11] B[3] C[11] C[3] 0 0 0 0 0 1 0 0 0 0 0 0 2 SEL_PDX PLL_PDX SEL_GAIN ALC_FR[2] ALC_TLIM[0] ALC_VMAX[2] ALC_GAIN[2] 1 FBCLK ADF_ADC_INV 0 EVR_GAIN[2] EVR_SOFTSW SEL_MCLKO[0] 0 SP_IDL[0] VD_DCTL1[2] FS[2] PLL_FCKI[2] LPF_HSF[2] A[10] A[2] B[10] B[2] C[10] C[2] 0 0 0 0 0 0 0 0 0 0 0 0 1 LO_PDX 0 SEL_IN[1] ALC_FR[1] ALC_RWT[1] ALC_VMAX[1] ALC_GAIN[1] 0 REC_ALC ADF_MODE[1] SEL_USE_DSP[1] EVR_GAIN[1] EVR_SSC[1] 0 0 SP_BIAS[1] VD_DCTL1[1] FS[1] PLL_FCKI[1] LPF_HSF[1] A[9] A[1] B[9] B[1] C[9] C[1] 0 0 0 1 1 0 0 0 0 0 0 0 0 SP_PDX VD_PDX SEL_IN[0] ALC_FR[0] ALC_RWT[0] ALC_VMAX[0] ALC_GAIN[0] 0 PB_ALC ADF_MODE[0] SEL_USE_DSP[0] EVR_GAIN[0] EVR_SSC[0] 0 SP_OUT_EN SP_BIAS[0] VD_DCTL1[0] FS[0] PLL_FCKI[0] LPF_HSF[0] A[8] A[0] B[8] B[0] C[8] C[0] 0 1 0 0 1 0 0 0 1 0 0 0
No.A0906-12/31
LC074146LP
Register Description
* Bold letters indicate initial settings.
ADRS 00h Bit [7] [6] [5] [4] [3] [2] [1] [0] 01h [7] [5:4] Name MIC_PDX MIC_PWR_PDX PGA_PDX ADC_PDX DAC_PDX SEL_PDX LO_PDX SP_PDX SYNC_CLR VREF_BIAS 00b [2] [0] 02h [5:4] [3] [1:0] 03h [7:5] [4:3] [2:0] 04h [7] [6] [5:4] [3:2] [1:0] 05h [5:0] PLL_PDX VD_PDX MIC_GAIN SEL_GAIN SEL_IN ALC_VAL ALC_FA ALC_FR ALC_FULLEN ALC_ZCD ALC_ZCDTM ALC_ATLIM ALC_RWT ALC_VMAX 0Eh 06h 08h [5:0] [7] [6] [5:4] [3] [2] [1:0] ALC_GAIN HSF_ON NOTCH_ON WIND_CUT AD_MUTE FBCLK REC_ALC PB_ALC 10b 0b 0b 01b 0b 01b 001b 11b 101b 0b 1b 00b 01b 10b Init 0b 0b 0b 0b 0b 0b 0b 0b 0b MIC amplifier circuit, power down Description 1:OFF (normal operation) 0:ON
MIC power circuit (MIC_PWR pin), power down 1:OFF (normal operation) 0:ON PGA circuit, power down ADC circuit, power down DAC circuit, power down 1:OFF (normal operation) 0:ON 1:OFF (normal operation) 0:ON 1:OFF (normal operation) 0:ON
Selector (ALC or DAC) circuit, power down 1:OFF (normal operation) 0:ON Line out circuit, power down Speaker amplifier circuit, power down Internal logic clear Reference voltage circuit (VREF pin) setting 00: Power down 11: Normal operation 10: Quick rise to reference voltage 01:IREF ON/VREF OFF PLL circuit, power down Video driver circuit, power down 1:OFF (normal operation) 0:ON 1:OFF (normal operation) 0:ON 1:OFF (normal operation) 0:ON 1:OFF (normal operation) 0:ON 1:ON 0:OFF (normal operation)
MIC amplifier circuit, gain setting 11: 26dB 10: 20dB 01: 0dB 00: Inhibited Selector circuit, gain setting 1: 6dB 0: 0dB Selector circuit, input setting 11, 00: Inhibited 10: ALC 01: DAC ALC circuit, ALC value (limiter level) setting ALC circuit, attack coefficient setting ALC circuit, recovery coefficient setting ALC circuit, full scale detection mode setting 1: ON 0: OFF ALC circuit, zerocross timing gain change 1: ON 0: OFF ALC circuit, zerocross detection timeout time setting ALC circuit, inter-zerocross attack limit setting ALC circuit, setting wait time when recovery ALC circuit, PGA(REC)/digital volume (PB) maximum gain setting 0Eh: 0dB 3Fh to 31h: Inhibited, 30h: +34dB to 00h: -14dB, 1dB step ALC circuit, manual mode PGA gain setting 0Eh: 0dB 3Eh to 31h: Inhibited, 30h: +34dB to 00h: -14dB, 1dB step 3Fh: MUTE HSF filter (high frequency shelf filter) attenuation side only 0: OFF 1: ON Notch filter 0: OFF 1: ON 00: OFF
0Eh 0b 0b 00b 0b 0b
Wind cut function(HPF f, operation) 11: 400Hz 10: 300Hz 01: 200Hz ADOUT output mute 0: OFF 1: ON BCLK FS setting 0: 64fs 1: 32fs ALC mode setting 10: REC_ALC, PB manual gain 01: PB_ALC, REC manual gain 00/11: ALCOFF, REC, PB manual gain ADF circuit, BCLK, LRCLK setting 1: Master mode 0: Slave mode ADF circuit, DAC input data setting 1: Inverted 0: Non-inverted ADF circuit, ADC output data setting 1: Inverted 0: Non-inverted
09h
[4] [3] [2] [1:0]
ADF_MASTER ADF_DAC_INV ADF_ADC_INV ADF_MODE SEL_USE_DSP
0b 0b 0b 00b
ADF circuit, format setting 11, 10: Right-justified 01: Left justified 00: I2S ADC/DAC path select, 11: Inhibited
0Ah
[1:0]
00b
10: ADC DSP absent, DAC DSP present (ADCADOUT, DAINDSPDAC) 01: Internal loopback (analog input/output) (ADCDSPADOUT/DAC) 00: ADC DSP present, DAC DSP absent (ADCDSPADOUT, DAINDAC)
0Bh
[7] [6:0]
EVR_MUTE EVR_GAIN
1b
EVR circuit, mute setting EVR circuit, gain setting
1: ON 0: OFF 00h: MUTE 3Fh: 0dB
00h
57h: +12dB to 2Ch: -9.5dB, 0.5dB step 2Bh: -10dB to 0Ch: -41dB, 1.0dB step 0Bh: -42dB to 00h: -64dB, 2.0dB step
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No.A0906-13/31
LC074146LP
Continued from precceding page.
ADRS 0Ch Bit [6] [5:4] [2] [1:0] Name EVR_ZCD EVR_ZCDTM EVR_SOFTSW EVR_SSC 00b 0Dh [3:2] SEL_MCLKO 00b 0Eh [7] [6] [5:4] [0] 0Fh [7] [6] [5:4] [3:2] [1:0] 10h [5] [4:3] LO_MUTE LO_VREFSW LO_GAIN SP_OUT_EN SP_TSD_EN SP_EXTBP_EN SP_EXTBP_G SP_IDL SP_BAIS VD_GAIN VD_CTL2 00b [2:0] VD_CTL1 010b 11h [4:0] FS 01000b 1b 1b 10b 0b 1b 0b 00b 10b 00b 0b Init 1b 01b 1b Description EVR circuit, gain change at zerocross timing 1: ON 0: OFF EVR circuit, zerocross detection time timeout time setting EVR circuit, soft switch function 1: ON 0: OFF
EVR circuit, Soft switch function time setting Value in parentheses ( ) denotes+12dBMUTE time. 11, 10: Inhibited 01: 2.278ms/step(200ms) 00: 1.142ms/step(100ms) MCLK output select (MCLKO pin) 00: "L"10: "H" 01, 11: MCLKIN or PLL [ADRS: 01h, D2 PLL_PDX: PLL prioritized output when set to 1] Line out circuit, mute setting 1: ON 0: OFF Line out circuit, connection to VREF setting 1: ON 0: OFF Line out circuit, gain select 11: 8dB 10: 6dB 01: 4dB 00: 0dB Speaker amplifier circuit, output enable 1: ON 0: OFF Speaker amplifier circuit, thermal shutdown enable 1: ON 0: OFF Speaker amplifier circuit, external input BEEP enable 1: ON 0: OFF Speaker amplifier circuit, external input BEEP gain select 11: -21dB 10: -18dB 01: -15dB 00: -12dB Speaker amplifier circuit, idling current setting 11: 2.0mA 10: 1.0mA 01: 0.67mA 00: 0.5mA Speaker amplifier circuit, bias voltage control setting 11: 0.833 10: 0.766 01: 0.666 00: 0.5 (*VDDana) VIDEO GAIN 1: +12dB 0: +6dB VIDEO input sync DC OFFSET setting (settings other than those listed below are disallowed.) 00/01/10: 0mV/62.5mV/125mV VIDEO input sync DC OFFSET setting (settings other than those listed below are disallowed.) 001/010/011/100/101: -12.5mV/0mV/12.5mV/25mV/37.5mV PLL FS setting (settings other than those listed below are disallowed.) 01000: 48 kHz/00111: 44.1kHz/00110: 32 kHz/00101: 24kHz/ 00100: 22.05kHz/00011: 16kHz/00010: 12 kHz/00001: 11.025kHz/ 00000: 8kHz/10000: 7.86113kHz/ to 11010: 7.87113kHz (+0.001kHz Step) PLL input clock setting (settings other than those listed below are disallowed.) 000: 12MHz, 001: 24MHz, 100: 13.5MHz, 101: 27MHz Gain setting 000/001/010/011/100/101/110/111: 0(OFF)/-2/-4/-6/-7/-8/-10/-12dB Notch filter coefficient setting Notch filter coefficient setting Notch filter coefficient setting Notch filter coefficient setting Notch filter coefficient setting Notch filter coefficient setting
12h 13h 14h 15h 16h 17h 18h 19h
[2:0] [2:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
PLL_FCKI HPF_HSF Notch_1[15:8] Notch_1[7:0] Notch_2[15:8] Notch_2[7:0] Notch_3[15:8] Notch_3[7:0]
000b 000b 00h 00h 00h 00h 00h 00h
PM MIC ALC ADC DAC EVR ADF
: Power Management : Microphone Amp : Automatic Level Control : AD Converter : DA Converter : Electronic Variable Resistor : Audio Data Format
PGA ADRS Init Lch Rch 2^n Nh Nb
: Programmable Gain Amplifier : Address : Initial Value : Left Channel : Right Channel : 2n (ex.2^10=1024) : N denotes a hexadecimal number. : N denotes a binary number.
No.A0906-14/31
LC074146LP
Register Details
Reference voltage generator circuit VREF_BIAS: Voltage Reference Bias
ADRS 01h Bit [5:4] Name VREF_BIAS 00b Init Description Sets the reference voltage circuit (VREF pin). 11: Normal operation (standard resistor value) 10: Quick rise to reference voltage <*1> 01: Activates IREF bias, VREF OFF 00: Power down
<*1> The target voltage is reached quickly by connecting a low-resistance element in the "reference voltage generation circuit." During normal operation, a standard resistance is recommended in order to save power. Logic synchronous clear SYNC_CLR: Synchronus Clear
ADRS 01h Bit [7] Name SYNC_CLR 0b Init Clears the internal logic circuit. 1: ON 0: OFF (normal operation) Used only when the operation of the logic circuit is unstable. Not used in normal operation. Description
Power down circuit MIC_PDX MIC_PWR_PDX PGA_PDX ADC_PDX DAC_PDX SEL_PDX
ADRS 00h Bit [7] [6] [5] [4] [3] [2] [1] [0] 01h [2] [0]
: Mic Amp Power Down : Microphone Power Power Down : Pga Power Down : Adc Power Down : Dac Power Down : Selcter Power Down
Name MIC_PDX MIC_PWR_PDX PGA_PDX ADC_PDX DAC_PDX SEL_PDX LO_PDX SP_PDX PLL_PDX VD_PDX Init 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b
LO_PDX SP_PDX PLL_PDX VD_REG_OFF VD_PDX
: Line-Out buffer Power Down : Speaker Amp Power Down : Pll Power Down : Video Driver Power Down : Video Power Down
Description
MIC amplifier circuit, power down function 1: OFF (normal operation) 0: ON MIC power supply circuit (MIC_Power pin), Power down function 1: OFF (normal operation) 0: ON PGA circuit, power down function 1: OFF (normal operation) 0: ON ADC circuit, power down function 1: OFF (normal operation) 0: ON DAC circuit, power down function 1: OFF (normal operation) 0: ON Selector (ALC or DAC) circuit, Power down 1: OFF (normal operation) 0: ON Line out circuit, power down function 1: OFF (normal operation) 0: ON Speaker amplifier circuit, power down function 1: OFF (normal operation) 0: ON PLL circuit, power down function 1: OFF (normal operation) 0: ON Video driver circuit, power down function 1: OFF (normal operation) 0: ON
In order to power save a relevant circuit that is not to be used, activate the power down mode. Microphone circuit MIC_GAIN: Microphone Amp Gain
ADRS 02h Bit [5:4] Name MIC_GAIN Init 01b Set the gain of the MIC amplifier circuit. 11: 26dB 10: 20dB 01: 0dB 00: Inhibited Description
No.A0906-15/31
LC074146LP
Recording System ALC Circuit Setting ALC_VAL ALC_FA ALC_FR ALC_FULLEN ALC_ZCD ALC_ZCDTM
ADRS 03h Bit [7: 5]
: Alc Value : Alc Factor Attack : Alc Factor Recovery : Alc Full Scale Detect Enable : Alc Zero Cross Detect : Alc Zero Cross Detect Time Out
Name ALC_VAL 001b Init
ALC_ATLIM ALC_RWT ALC_VMAX ALC_GAIN ALC_MODE
: Alc Attack Limit : Alc Recovery Waiting Time : Value Max : Pga Gain at Manual Mode : Alc_Mode
Description
Set the ALC limiter level of the ALC circuit. 000: -3dBFS 001: -4dBFS 010: -5dBFS 011: -6dBFS 100: -7dBFS 101: -8dBFS 110: -9dBFS 111: -10dBFS Set the attack coefficient of the ALC circuit. FA[1:0] 11b 00 01 10 11 1dB attenuation time 1/fs 2/fs 4/fs 8/fs fs=8kHz 125s 250s 500s 1ms fs=48kHz 20.83s 41.67s 83.33s 166.7s @fs -1dB -0.5dB -0.25dB -0.125dB
[4: 3]
ALC_FA
[2:0]
ALC_FR
Set the recovery coefficient of the ALC circuit. FR[2:0] 000 001 101b 010 011 100 101 110 111 1dB boost time 128/fs 256/fs 512/fs 1024/fs 2048/fs 4096/fs 8192/fs 16384/fs fs=8kHz 16ms 32ms 64ms 128ms 256ms 512ms 1024ms 2048ms fs=48kHz 2.67ms 5.33ms 10.67ms 21.33ms 42.67ms 85.33ms 170.7ms 341.3ms @fs -2-7dB -2-8dB -2-9dB -2-10dB -2-11dB -2-12dB -2-13dB -2-14dB
04h
[7]
ALC_FULLEN 0b
Sets the full scale detection mode of the ALC circuit. 1: Performs attack operation regardless of the ALCZCD setting when a full scale is detected. 0: Normal operation Controls the gain change operation of the ALC circuit at zerocross timing. 1b 1: Changes the gain at zerocross timing. 0: Changes the gain without waiting for a zerocross timing. Set the zerocross detection timeout time of the ALC circuit. 00b 11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs Valid when [ALC_ZCD]=1. Set the limit number of attack operation of the ALC circuit during the zerocross interval. Limit attenuation ATLIM[1:0] 01b 00 01 10 11 Number 2 4 8 16 FA=00 2dB 4dB 8dB 16dB FA=01 1dB 2dB 4dB 8dB FA=10 0.5dB 1dB 2dB 4dB FA=11 0.25dB 0.5dB 1dB 2dB
[6]
ALC_ZCD
[5:4]
ALC_ZCDTM
[3: 2]
ALC_ATLIM
Valid when [ALC_ZCD]=1. [1:0] ALC_RWT Set the recovery operation wait time of the ALC circuit RWT[1:0] 00 10b 01 10 11 512/fs 1024/fs 2048/fs 64ms 128ms 256ms 10.67ms 21.33ms 42.67ms Wait time 256/fs fs=8kHz 32ms fs=48kHz 5.33ms
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No.A0906-16/31
LC074146LP
Continued from precceding page.
ADRS 05h Bit [5:0] Name ALC_VMAX Init 3Fh to 31h: Inhibited 30h: +34dB 0Eh 2Fh: +33dB : : <== 1dB increment 01h: -13dB 00h: -14dB 06h [5:0] ALC_GAIN Set the manual mode PGA gain of the ALC circuit (Init value = 0Eh: 0dB). 3Fh: MUTE 3Eh to 31h: Inhibited 0Eh 30h: +34dB 2Fh: +33dB : : <== 1dB increment 01h: -13dB 00h: -4dB 08h [1:0] REC_ALC PB_ALC 10h Set the ALC mode. 10: REC ALC, PB manual gain setting 01: PB ALC, REC manual gain setting 00/11: ALC OFF, REC, PB manual gain setting Description Set the maximum PGA gain of the ALC circuit (Init value = 0Eh: 0dB).
See the section on "Description of ALC Operation." ALC Circuit Gain Setting Table ALC_VMAX[5:0]/ALC_GAIN[5:0]
[5:0] 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H GAIN -14dB -13dB -12dB -11dB -10dB -9dB -8dB -7dB -6dB -5dB [5:0] 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H GAIN -4dB -3dB -2dB -1dB 0dB 1dB 2dB 3dB 4dB 5dB [5:0] 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH GAIN 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 15dB [5:0] 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H GAIN 16dB 17dB 18dB 19dB 20dB 21dB 22dB 23dB 24dB 25dB [5:0] 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H GAIN 26dB 27dB 28dB 29dB 30dB 31dB 32dB 33dB 34dB
Digital EVR Circuit Setting EVR_MUTE : Evr Mute EVR_GAIN : Evr Gain EVR_ZCD : Evr Zero Cross Detect
ADRS 0Bh Bit [7] [6:0] Name EVR_MUTE EVR_GAIN 00h Init 1b
EVR_ZCDTM : Evr Zero Cross Detect Time Out EVR_SOFTSW : Evr Soft Switch EVR_SSC : Evr Soft Switch Time Control
Description Controls the mute function of the EVR (digital) circuit. 1: ON 0: OFF Set the gain of the EVR (digital) circuit. 3Fh: 0dB 57h: +12dB to 2Ch: -9.5dB/0.5dB step 2Bh: -10dB to 0Ch: -41dB/1.0dB step 0Bh: -42dB to 00h: -64dB/2.0dB step
0Ch
[6]
EVR_ZCD 1b
Controls the gain change operation of the EVR (digital) circuit at zerocross timing. 1: Changes the gain at the zerocross timing. 0: Changes the gain without waiting for a zerocross timing. Set the zerocross detection timeout time of the EVR (digital) circuit. 01b 11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs Valid when [ALC_ZCD]=1 Controls the soft switch function of the EVR (digital) circuit. 1: ON 0: OFF Set the time of the soft switch function of the EVR (digital) circuit (dos not depend on fs). 00b 11, 10: Inhibited 01: 2.278ms/step, (200ms: When +12dBMUTE) 00: 1.142ms/step, (100ms: When +12dBMUTE)
[5:4]
EVR_ZCDTM
[2] [1:0]
EVR_SOFTSW EVR_SSC
1b
No.A0906-17/31
LC074146LP
Digital EVR Circuit Gain Setting Table EVR_GAIN [6:0]
[6:0] 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H GAIN -64dB -62dB -60dB -58dB -56dB -54dB -52dB -50dB -48dB -46dB -44dB -42dB -41dB -40dB -39dB -38dB -37dB -36dB [6:0] 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H GAIN -35dB -34dB -33dB -32dB -31dB -30dB -29dB -28dB -27dB -26dB -25dB -24dB -23dB -22dB -21dB -20dB -19dB -18dB [6:0] 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H GAIN -17dB -16dB -15dB -14dB -13dB -12dB -11dB -10dB -9.5dB -9dB -8.5dB -8dB -7.5dB -7dB -6.5dB -6dB -5.5dB -5dB [6:0] 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H GAIN -4.5dB -4dB -3.5dB -3dB -2.5dB -2dB -1.5dB -1dB -0.5dB +0dB +0.5dB +1dB +1.5dB +2dB +2.5dB +3dB +3.5dB +4dB [6:0] 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H GAIN +4.5dB +5dB +5.5dB +6dB +6.5dB +7dB +7.5dB +8dB +8.5dB +9dB +9.5dB +10dB +10.5dB +11dB +11.5dB +12dB
Audio Data Formats FBCLK : Audio Data Format BCLK ADF_MASTER : Audio Data Format Master Mode MCLK_DIV : Master Clock Divide
ADRS 08h 09h Bit [2] [4] FBCLK ADF_MASTER 0b [3] [2] [1:0] ADF_DAC_INV ADF_ADC_INV ADF_MODE 0b 0b 00b Name Init 0b
ADF_DAC_INV : Audio Data Format Dac Data Invert ADF_ADC_INV : Audio Data Format Adc Data Invert ADF_MODE : Audio Data Format Mode
Description
Sets the BCLK frequency of the ADF circuit. 1: 32fs 0: 64fs ADF circuit 1: Master mode, BCLK and LRCLK pins are set for output. 0: Slave mode, BCLK and LRCLK pins are set for input. Sets the DAC input data of the ADF circuit. 1: Inverted 0: Non-inverted Sets the ADC output data of the ADF circuit. 1: Inverted 0: Non-inverted Define the data format of the ADF circuit. 11, 10: Right justification 01: Left justification 00: I2S
See the section on "Audio Data Formats." DSP Related Settings HSF_ON : High Frequency Shelf Filter ON NOTCH_ON : Notch Filter ON WIND_CUT : Wind_Cut Filter
ADRS 08h Bit [7] [6] [5:4] 13h [2:0] Name HSF_ON NOTCH_ON WIND_CUT HPF_HSF 000b 14h 15h 16h 17h 18h 19h [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Notch_1[15:8] Notch_1[7:0] Notch_2[15:8] Notch_2[7:0] Notch_3[15:8] Notch_3[7:0] 00h 00h 00h 00h 00h 00h Init 0b 0b 00b
NOTCH_1 : Notch Factor 1 NOTCH_2 : Notch Factor 2 NOTCH_3 : Notch Factor 3
Description
HSF circuit attenuation side only 1: ON 0: OFF Sets the notch filter. 1: ON 0: OFF WIND_CUT function (HPF fc setting) 11: 400Hz 10: 300Hz 01: 200Hz 00: OFF Set the HSF gain (gain at the 1/2fs point). 000: 0dB/001: -2dB/010: -4dB/011: -6dB/ 100: -7dB/101: -8dB/110: -10dB/111: -12dB Notch filter coefficient setting Notch filter coefficient setting Notch filter coefficient setting Notch filter coefficient setting Notch filter coefficient setting Notch filter coefficient setting
No.A0906-18/31
LC074146LP
Line Out Circuit LO_MUTE : Line Out Mute LO_VREFSW : Line Out Voltage Reference Switch
ADRS 0Eh Bit [7] [6] Name LO_MUTE LO_VREFSW 1b [5:4] LO_GAIN 10b Init 1b
LO_GAIN : Line Out Gain
Description
Controls the mute function of the line out circuit. 1: Enables MUTE function. 0: Disables MUTE function. Sets the line out circuit. 1: Connects to the reference power source(VREF). 0: Does not connect to the reference power source (VREF). Select the gain of the line out circuit. 11: 8dB 10: 6dB 01: 4dB 00: 0dB
Speaker Amplifier Circuit SP_OUT_EN : Speaker Out Enable SP_TSD_EN : Speaker Tsd Enable SP_EXTBP_EN : Speaker External Beep Enable
ADRS 0Eh 0Fh Bit [0] [7] [6] [5:4] [3:2] [1:0] Name SP_OUT_EN SP_TSD_EN SP_EXTBP_EN SP_EXTBP_G SP_IDL SP_BIAS Init 0b 1b 0b 00b 10b 00b 1: ON 0: OFF Enables or disables the thermal shutdown function of the speaker amplifier circuit. 1: ON 0: OFF Enables or disables the external input beep function of the speaker amplifier circuit. 1: ON 0: OFF Select the external input beep gain of the speaker amplifier circuit. 11: -21dB 10: -18dB 01: -15dB 00: -12dB Set the idling current of the speaker amplifier circuit. 11: 2.0mA 10: 1.0mA 01: 0.67mA 00: 0.5mA Set the bias of the speaker amplifier circuit. 11: 0.833*AVDD 10: 0.766*AVDD 01: 0.666*AVDD 00: 0.5*AVDD
SP_EXTBP_G : Speaker External Beep Gain SP_IDL : Speaker Idle Current SP_BIAS : Speaker Bias
Description
Enables or disables the speaker amplifier circuit.
See the section on "Speaker Amplifier (SP_AMP) Start/Stop Sequence." Video Circuit
ADRS 10h Bit [5] [4:3] [2:0]
* See the section on the video circuit. VD_CTL: Video Driver Control
Init 0b 00b Selects the driver gain of the video circuit. 0: 6dB 1: 12dB Select the Input Sync Level DC OFFSET2 of the video circuit. 00: 0mV/01: 62.5mV/10: 125mV 11: Inhibited Select the Input Sync Level DC OFFSET1 of the video circuit. 010b 001: -12.5mV/010: 0mV/011: 12.5mV/100: 25mV/101: 37.5mV 000/110: Inhibited Description Name VD_GAIN VD_CTL2 VD_CTL1
VD_GAIN: Video Driver Gain
Video Driver Sync DC Level Adjustment Table
VD_CTL2[1] 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VD_CTL2[0] 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 VD_CTL1[2] 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 VD_CTL1[1] 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 VD_CTL1[0] 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 Input_Sync_Dc -12.5mV 0mV 12.5mV 25.0mV 37.5mV 50.0mV 62.5mV 75.0mV 87.5mV 100.0mV 112.5mV 125.0mV 137.5mV 150.0mV 162.5mV Output_Sync_Dc 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV
No.A0906-19/31
LC074146LP
Loopback Circuit SEL_USE_DSP: Select Use Dsp
ADRS 0Ah Bit [1:0] Name SEL_USE_DSP 00b Init Set the DSP path of the loopback circuit. 11: Inhibited 10: ADC through, DSP exists in the DAC path (ADCADOUT, DAINDSPDAC) 01: Internal loopback (analog input/output) (ADCDSPADOUT/DAC) 00: DSP exists in the ADC path, DAC through (ADCDSPADOUT, DAINDAC) Description
See the section on the loopback. PLL Circuit SEL_MCLKO : Select Mclk Output MCLKDIV : Mclk Divide
ADRS 0Dh Bit [3:2] Name SEL_MCLKO 00b Init 00: "L" 10: "H" 01/11: MCLKIN or DIV2(PLL) [ADRS01h, D2 PLL_PDX: DIV2 (PLL) output takes precedence when set to 1.] 11h [4:0] PLL_FS 01000b PLL FS setting 01000: 48kHz/00111: 44.1kHz/00110: 32kHz/00101: 24kHz/ 00100: 22.05kHz/00011: 16kHz/00010: 12kHz/00001: 11.025kHz/ 00000: 8kHz/10000: 7.86113kHz/to 11010: 7.87113kHz (+0.001kHz step) 12h [2:0] PLL_FCKI 000b Set the MCLKIN input frequency of the PLL circuit. 000: 12MHz 001: 24MHz 100: 13.5MHz 101: 27MHz
PLL_FS : Pll Frequency Sampling PLL_FCKI : Pll
Description Select the output (MCLKO pin) of the PLL circuit.
See the section on the PLL configuration. PLL Sampling Frequency Setting
FS[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 fs(kHz) 8 11.025 12 16 22.05 24 32 44.1 48 FS[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 fs(kHz) 7.86113 7.86213 7.86313 7.86413 7.86513 7.86613 7.86713 7.86813 7.86913 7.87013 7.87113
IC Test Settings Must always be fixed to initial values. Note: Addresses TEST1-TEST12 must be set in the order of 1Ah to 25h.
ADRS 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h Bit [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Name TEST1[7:0] TEST2[7:0] TEST3[7:0] TEST4[7:0] TEST5[7:0] TEST6[7:0] TEST7[7:0] TEST8[7:0] TEST9[7:0] TEST10[7:0] TEST11[7:0] TEST12[7:0] Init 00h 01h 00h 02h 03h 10h 00h B0h 21h 00h 00h 00h Description For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value. For IC testing. Must always be fixed to the initial value.
No.A0906-20/31
LC074146LP
Specification Details
* Power save/system reset When the PDNB pin is set to 0, all the circuits are set to power down mode regardless of the power down settings for each block. A 0 on the PDNB pin also triggers a system reset. After the power is first applied, the system must be reset without fail. (Refer to checkpoint (2) on page 30.) After resetting, the contents of the serial port register are initialized. The VREF buffer is activated by releasing power down mode by setting the PDNB pin from 0 to 1, and then by setting VREF_BIAS[1:0] to 01. When VREF_BIAS [1:0] is set to 10, VREF starts. Along with the start of VREF, the LINE output pin is biased to 1/2VDDA. Once the VREF voltage has stabilized, VREF_BIAS [1:0] must be set to 11 (normal state). * Microphone (MIC) amplifier The microphone amplifier has a differential input and a gain of +26dB (typ). Its gain can also be set to +20 dB or 0 dB by register MGAIN [1:0]. Its input resistance is 70k (typ). The MICPWR is a power output pin for the microphone, and its output voltage is 2.3V (typ 0.767*VDDA). The maximum output current is 20mA. The microphone amplifier is placed in the power down mode by setting MIC_PDX to 0. When MIC_PWR_PDX is set to 0, the microphone power supply circuit is placed in the power down mode. * Recording system automatic level control (ALC) The amplifier gain of the PGA (Programmable Gain Amplifier) must be automatically adjusted so that the A/D converter output audio level is setup to the predetermined value. The gain can be varied within a range (maximum) of -14dB to +34dB. When using ALC in the recording system, set REC_ALC to 1 and PB_ALC to 0 (recording system ALC mode). When REC_ALC is set to 0 and PB_ALC is set to 0 (ALC off mode), the PGA is placed in the manual mode, and the amplifier gain is fixed to the value of the ALC_GAIN register setting. When PGA_PDX is set to 0, the PGA is placed in the power down mode. During normal use, the state of PGA_PDX must be switched at the same time as ADC_PDX. For further details on operation, refer to "Description of ALC/limiter (Automatic Level Control) operation." Any of eight recording ALC levels (in 1dB steps from -3dBFS to -10dBFS) can be set using the ALC_VAL register. * A/D converter This converts the analog PGA output signals into digital data, which is then output as 16-bit serial audio data. Three formats are supported: I2S, Left-justified mode, Right-justified mode. A 1st order analog low-pass filter is incorporated for anti-aliasing. When ADC_PDX is set to 0, the A/D converter block is placed in the power down mode. The 100/fs period following the release of the power down mode is the A/D converter initialization period, and the data are output as 0. When the power is first applied and when the system clock is switched, the converter must be initialized. A digital high-pass filter for canceling DC offset is incorporated. The filter's cut-off frequency fc is 0.94Hz (at fs=48kHz). 0dBFS is equivalent to 0.6 *VDDA. * D/A converter This converts the digital 16-bit serial audio data into analog signals. Three formats are supported: I2S, left justification and right justification. When DAC_PDX is set to 0, the D/A converter block is placed in the power down mode. When the power down mode is released, the converter is initialized. When the power is first applied and when the system clock is switched, the converter must be initialized. 0dBFS is equivalent to 0.6 *VDDA.
No.A0906-21/31
LC074146LP
* Digital volume Contained inside the D/A converter is a digital volume control, and by setting EVR_GAIN [6:0], the gain level can be attenuated from +12dB (max) to -64dB or muted. When EVR_ZCD is 0, the gain is changed immediately after setting EVR_GAIN [6:0]. When EVR_ZCD is 1, after setting EVR_GAIN [6:0] the gain is changed at the zero cross timing of the audio signals. The timeout time for zero cross detection can be set using EVR_ZCDTM [1:0]. When EVR_SOFTSW is 1, the soft switching operation is performed, and after the EVR_GAIN [6:0] setting has been changed, the gain automatically changes in 1-step increments until it arrives at the predetermined value. The period of gain change can be set using EVR_SSC [1:0]. If EVR-SOFTSW is set to 1 and EVR_ZCD is set to 1, the D/A converter, after the lapse of the time defined by EVR_SSC[1:0], repeats the cycle of waiting for the next zero cross point and changing the gain by 1 increment, until the predetermined volume value is reached. * Playback system automatic level control (ALC) When REC_ALC is set to 0 and PB_ALC is set to 1 (playback system ALC mode), the digital volume control functions as the playback system ALC. Subject the volume value to automatic adjustment so that the digital volume output level is set to the predetermined value. For further details on operation, refer to "Description of ALC/limiter (automatic level control) operation." When REC_ALC is set to 0 and PB_ALC is set to 0 (ALC off mode), the digital volume control is set to manual mode, and the gain is fixed to the EVR_GAIN [6:0] register setting. Programmable Digital Filter
ADC DACIN decimation filter ADOUT DAC
HSF(LPF)
HPF
notch
* High-pass filter (HPF, 1st order) WIND_CUT [5:4] turns off the high-pass filter (through) when initialized to (00). Regardless of the sampling frequency (fs), the cutoff frequency (fc) is 400 Hz when WIND_CUT [5:4] is set at 11, 300Hz at 10, 200Hz at 01 and OFF at 00. * Programmable digital high frequency shelf filter (HSF) Attenuation range only of HSF (same as low-pass filter) This is a 2nd-order biquad type of filter, and its attenuation amount at 1/2fs can be set to 0, -2, -4, -6, -8, -10 or -12dB.
HSF filter HSF filter ON/OFF HSF filter gain setting Name HSF_ON HPF_HSF ADRS 08h 13h bit [7] [2:0] 0: OFF 1: ON 000: 0dB, 001: -2dB, 010: -4dB, 011: -6dB 100: -7dB, 101: -8dB, 110: -10dB, 111: -12dB Description
* Notch filter This is a 2nd-order biquad type of filter, and its coefficients are set using the register. Specify the sampling frequency (fs), cut-off frequency (fc) and bandwidth (fd), and load coefficients a, b and c represented in 16-bit 2's complement format in the register.
Notch filter Notch filter ON/OFF Notch_1 coefficient setting (1) Notch_1 coefficient setting (2) Notch_2 coefficient setting (1) Notch_2 coefficient setting (2) Notch_3 coefficient setting (1) Notch_3 coefficient setting (2) Name NOTCH_ON Notch_1[15:8] Notch_1[7:0] Notch_2[15:8] Notch_2[7:0] Notch_3[15:8] Notch_3[7:0] ADRS 08h 14h 15h 16h 17h 18h 19h bit [6] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0: OFF 1: ON Coefficient a setting Coefficient a setting Coefficient b setting Coefficient b setting Coefficient c setting Coefficient c setting Description
No.A0906-22/31
LC074146LP
* Line amplifier The line amplifier provides a gain of 0, 4, 6 or 6dB. When LO_MUTE is set to 1, the line output is muted. When LO_PDX is set to 0, the line amplifier is placed in the power down mode. If the line output is set to the high-impedance state when the line amplifier is placed in the power down mode, LO_VREFSW must be set to 0.
LINE OUT Power down Mute Connection to VREF Gain select Name LO_PDX LO_MUTE LO_VREFSW LO_GAIN ADRS 00h 0Eh 0Eh 0Eh bit [1] [7] [6] [5:4] Description 0: Power down 1: Power up 0: Disables MUTE. 1: Enables MUTE. 0: Does not connect to VREF. 1: Connects to VREF*. 00: 0dB, 01: 4dB, 10: 6dB, 11: 8dB
* It is not possible to connect between LINE OUT and VREF by setting LO_VREFSW to 1 even if LO_PDX is set to 1. * Speaker amplifier The speaker amplifier must be started after the selector amplifier output (LOUT2) has been activated and the voltage has stabilized. Either 0dB or +6dB can be selected as the selector amplifier gain using the SEL_GAIN setting. VDDS in the range of 2.7V to 5.5V is supported. (Piezoelectric speaker supported) The amplifier gain is 6dB (+12dB with the BTL output). (With an 8 load) The SPKIN input resistance is 10 k (type). The gain from the BEEP input to BTL output can be varied within the range of -12dB to -21dB using the SP_EXTBP_G [1:0] setting. When SP_PDX is set to 0, the speaker amplifier is placed in the power down mode. Depending on VDDS, one of the four speaker terminal voltages (1.5V, 2V, 2.3V and 2.5V) can be selected using SP_BAIS [1:0] to achieve an optimal dynamic range. (At VDDA=3V) * Thermal shutdown If a chip temperature of 140C or higher is detected while SP_TSD_EN is set 1, the speaker amplifier is placed in the power down mode for protection. The thermal shutdown function is disabled if SP_TSD_EN is set to 0.
SPEAKER AMP Power down mode Output enable Thermal shutdown External BEEP input BEEP gain select Idling current setting Bias voltage setting Name SP_PDX SP_OUT_EN SP_TSD_EN SP_EXTBP_EN SP_EXTBP_G SP_IDL SP_BIAS ADRS 00h 0Eh 0Fh 0Fh 0Fh 0Fh 0Fh bit [0] [0] [7] [6] [5:4] [3:2] [1:0] Description 0: Power down 1: Power up 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 00: -12dB, 01: -15dB, 10: -18dB, 11: -21dB 00: 0.5mA, 01: 0.67mA, 10: 1.0mA, 11: 2.0mA 00: 0.5, 01: 0.666, 10: 0.766, 11: 0.833 (*VDDA)
* PLL (a) PLL mode (PLL_PDX=1) In this mode, the 256fs clock (MCLK) used by the CODEC block is generated from the clock (12, 13.5, 24 and 27MHz frequencies supported) which is input from MCLK, and BCLK and LRCK are output. Sampling frequencies (fs) of 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz and 48kHz are supported. (b) EXT mode (PLL_PDX=0) In this mode, the 256fs clock (MCLK) from MCLKIN is input and used. When ADF_MASTER is 1, BCLK and LRCK whose frequency is obtained by dividing the frequency of MCLKIN are output. When ADF_MASTER is 0, BLCK and LRCK are external inputs. * In the CODEC block, BCLK and LRCK must be synchronized with MCLK. In PLL mode (PLL_PDX=1), operation must be performed in BCLK output mode (ADF_MASTER=1). In EXT mode (PLL_PDX=0) and when ADF_MASTER is 0, BCLK and LRCK synchronized with MCLK must be input.
No.A0906-23/31
LC074146LP
PLL Block Diagram
SEL_MCLKO[1:0] PLL_FCKI[2:0] FS[4:0] MCLKIN 24MHz 12MHz or 13.5MHz 27MHz 1/2 1/1 PLL PLL_PDX EXT PLL 1/8(32fs) FBCLK 1/4(64fs) 1/256 CODEC H L MCKOUT
ADF_MASTER
* Loopback
LRCK BCLK
(a) Loopback mode (SEL_USE_DSP [1:0] =01) Connect between ADOUT and DAIN. This enables the MIC input to be output to the line or speaker without recording or playback operation. In this case, external output through ADOUT is enabled but external input through DAIN is disabled. (b) Standard mode (SEL_USE_DSP [1:0] =00 or 10) The DAIN external input is enabled and the internal switch for ADOUT and DAIN is released.
ADOUT IF DAIN
SEL_USE_DSP[1:0] 00 01 10 11 ADC ADC ADC ADC ADC
Signal Path ->DSP ->ADC_Dout ->DSP ->ADC_Dout ->DSP ->DAC ->--->ADC_Dout ->DSP ->DAC DAC_Din ->--->DAC
Description of Function ADC, DAC parallel operation DSP inserted in REC (ADC) side ADC, DAC loopback operation DAC_Din input disabled ADC, DAC parallel operation DSP inserted in PB (DAC) side Inhibited side
Application (Uses) DSP function exists in REC (ADC) Analog input/output, DSP function test SDP function exists in PB(DAC) side
Note: The LPF, wind cut and notch functions serve as the DSP functions.
No.A0906-24/31
LC074146LP
* Video driver
REG VREF2 VREF1 0dB VIN VIN Sync DC (-12.5mV to 162.5mV) (12.5mV/step) is adjustable to VOUT Sync DC (100mV) ATT -6dB/0dB 0V CTL (VD_GAIN ) 75 LPF 12dB VOUT
Either 6dB or 12dB can be selected as the total gain of the video amplifier using the internal register setting (VD_GAIN). When the input sync level is within the -12.5mV to 162.5mV range, the output sync level can be adjusted to 0.1V using the internal register settings (VD_CTL1 [2:0] and VD_CTL2 [1:0]). Description of ALC/Limiter (automatic level control) operation Note: [xxxx] denotes a register name, and whatever is contained inside the parentheses " " is applicable in the PB-ALC mode. The amplifier gain "digital volume value" of the PGA (programmable gain amplifier) is automatically adjusted so that the A/D converter output audio level "digital volume output" is set to the ALC value [ALC_VAL [2:0]]. The PGA "digital volume" gain can be varied in the -14dB to +34dB range. The maximum value [ALC_VMAX [5:0]] can be set in this variable range. => If [ALC_VMAX [5:0]] is set to the maximum value of +34dB, the ALC functions can be used to the maximum. => If [ALC_VMAX [5:0]] is set to +0dB, it will no longer be possible to increase the gain in the "+" direction so the ALC function will work in the same way as a limiter. * ALC settings (a) Power-saving function When [PGA_PDX] is 0, the ALC circuit and PGA circuit are set to power down mode. (b) Manual function When both [REC_ALC] and [PB_ALC] are 0, manual mode is established. In the REC_ALC mode, the PGA gain is fixed at the manual mode value [ALC_GAIN [5:0]]. In the PB_ALC mode, the digital volume level is fixed at [EVR_GAIN [6:0]]. (c) System operation ALC is performed by feeding back the A/D converter "digital volume" data. Accordingly, configure the settings as shown in the table below in order for the ALC functions to be activated.
REC-ALC PGA_PDX ALCOFF ADC_PDX DAC_PDX REC_ALC PB_ALC 1 0 1 x 1 0 PB-ALC 0 0 x 1 0 1
No.A0906-25/31
LC074146LP
* Description of ALC operation The ALC has two types of operation, "attack" and "recovery." Refer to the operation diagrams on the next page. (1) Attack operation When the A/D converter "digital volume" output exceeds the ALC value [ALC_VAL [2:0]], the PGA gain "digital volume value" is reduced at a rate determined by the attack coefficient [ALC_FA [1:0]]. When zero cross detection [ALC_ZCD] is set to 1, the gain attenuation from zero cross to zero cross is limited by the limit value [ALC_ATLIM [1:0]]. (2) Recovery operation When the A/D converter "digital volume" output is within 2 dB of the ALC value [ALC_VAL[1:0]] and this status continues for the recovery wait time [ALC_RWT [1:0]], the PGA gain "digital volume value" is increased at a rate determined by the recovery coefficient [ALC_FR [2:0]]. This increase in the PGA gain "digital volume value" continues while the output remains within 2dB of the ALC value [ALC_VAL [1:0]]. The maximum increase in the PGA gain "digital volume value" from zero cross to zero cross is 1dB. Functions common to (1) and (2) * Zero cross detection When [ALC_ZCD] is set to 0, the PGA gain "digital volume value" changes regardless of the zero cross timing of the A/D converter "digital volume" output. When [ALC_ZCD] is set to 1, the PGA gain "digital volume value" changes at the zero cross timing of the A/D converter "digital volume" output. * Zero cross timeout A zero cross signal is generated internally if there is no zero cross signal during the zero cross timeout value [ALC_ZCDTM [1:0]] even when the PGA gain "digital volume" output is not zero-crossed. * Average output amplitude control The average output amplitude is reduced by spike and other noises in an attach operation. To prevent this, the recovery rate is automatically increased above the [ALC_FR [2:0]] setting value when there is an excessively high input in a short period of time.
No.A0906-26/31
LC074146LP
ALC Wave Forms
[ALC_VAL] Input signals
Post-PGA signals
[ALC_VAL] 2dB
a
b
c
d
e [ALC_VAL]
tSN: short period(e.g.. Spike Noise) Input signals
Post-PGA signals
[ALC_VAL] -2dB
Region a, A b, B c, C d, ,D e, E Attack Stable
Operation
PGA Gain Sudden attenuation Constant Constant Slow increase Faster increase than d Constant
Related Registers [ALC_FA] attack coefficient [ALC_VAL] ALC value [ALC_RWT] recovery wait time [ALC_FR] recovery coefficient [ALC_VMAX] PGA gain maximum value
Wait for recovery Recovery Recovery Stable
Limiter operation (maximum gain value [ALC_VMAX] set to 0dB)
[ALC_VAL] Input signals
Post-PGA signals a b c d tS a b
[ALC_VAL] 2dB
In the tS region, the "input" and "post-PGA" signal levels are the same. (Signal level through)
No.A0906-27/31
LC074146LP
VREF/line out start/stop sequence
BIAS circuit on BIAS charge LINE MUTE BIAS discharge BIAS circuit off
Power down VREF_BIAS1 VREF_BIAS0 PDNB LO_PDX LO_VREFSW LO_MUTE
LINE output
Power down
t1
t2
t2
t1 1/2VDDA
LOUT1
* Recommended values t1 = 300ms or more (when external capacitance connected to VREF is 1F) t2 = 1ms or more
Speaker Amplifier Startup Sequence
BIAS mode (standby) SPK power down BIAS started SPK power down BIAS started
SPK operation active
SPK operation active
SP_PDX SP_OUT_EN
t1
t2
t2 No time limit 1/2VDD
SPOUTP SPOUTN
* Recommended values t1 = 40ms or more (when external capacitance connected to SPKIN is 0.1F) t2 = 10ms or more * SP_OUT_EN, SPK_PDX must be set to 0 when the SPK is placed in the power down mode.
No.A0906-28/31
LC074146LP
ADC Decimation Filter
ADC Digital Filter Frequency Characteristics 20 0 -20 -40
gain [dB] gain [dB]
ADC Digital Filter Frequency Characteristics (passband) 1.0 0.8 0.6 0.4 0.2 -0.0 -0.2 -0.4
-60 -80 -100 -120 -140 0.0
-0.6 -0.8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -1.0 0.0 0.1 0.2 Frequency [fs] 0.3 0.4
Frequency [fs]
DAC Interpolation Filter
DAC Digital Filter Frequency Characteristics 0 0 -20 -40
gain [dB]
DAC Digital Filter Frequency Characteristics (passband)
-0.01 -0.02 -0.03
gain [dB]
-0.04 -0.05 -0.06 -0.07 -0.08
-60 -80 -100 -120 -140 0.0
-0.09 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -0.1 0.0 0.1 0.2 Frequency [fs] 0.3 0.4
Frequency [fs]
High_Pass_Filter
HSF_Filter
No.A0906-29/31
LC074146LP
Checkpoints
The user is responsible for ascertaining whether this IC can be adopted for the set to be mass production by the user, including the various condition for mounting in the set. 1) Power supply * The 3.0V type and 3.0V/5.0V type are available as the power supply pins. 3.0V type: Digital power supply (VDD), analog power supplies (VDDA, VDDV, VDDP) 3.0V/5.0V type: Analog power supply (VDDS) * The power-on sequence is such that the power is first applied in sequence starting with the circuits that operate using a high voltage and the power is turned off in sequence starting with the circuits that operate using a low voltage. 2) Resetting * At power-on, the PDNB pin must be set to low without fail. (A) or (B) is executed as shown in the figure below.
95% power level Normal operation level
Power pin tD
PDNB (A)
0.8V tD
PDNB tD>1s (B)
0.8V
Notes: (A) is reset at the same time as the power is first applied. (B) is reset immediately after the power is first applied. The MCLKIN pin clock input must be provided without fail during either the (A) or (B) period. 3) 3-line serial setting * Whenever 3-line serial setting is to be performed, it must be done where the MCLKIN input has stabilized without fail. * If garbled data is found, restart the IC (switching the state of the PDNB pin from low to high) and perform 3-line serial setting again.
No.A0906-30/31
LC074146LP
Sample Application Circuit
ASIC DVDD 10F
30 ADOUT 29 DAIN 28 DVDD 27 DVSS 26 TESTIN
25 GPORT1
24 GPORT0
23 SDA
22 SCK
21 CSB PDNB 20 VIDEOVREF 19 VIDEOOUT 18
31 LRCK 32 BCLK
1F VIDEO-OUT 75
33 MCLKO 34 MCLKIN 35 VSSP 36 VDDP
VSSV 17 VDDV 16 VIDEOIN 15
10F VDDv VIDEO-IN
10F 0.01F 0.1F 1.2k 1F
37 VCOFIL 38 VSSSUB 39 ALCIN MICINN MICINP LOUT1 LOUT2 MICPWR SPKIN 40 MICOUT
SPOUTP 14 VSSS 13
10F
VDDS 12 SPOUTN 11 VDDA VSSA BEEP VREF
VDDs
1
2
3
4
5
6
7
8
9
10
0.1F 2.2k to 4.7k AVDD
0.47F 0.47F
1F 1F 10F 0.1F
4700pF
MIC
LINEOUT
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of October, 2007. Specifications and information herein are subject to change without notice.
PS No.A0906-31/31

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